1 UT54ACS08E/ut54acts08e quadruple 2-input and gates july 2013 www.aeroflex.com/logic features ? 0.6 ? m crh cmos process - latchup immune ? high speed ? low power consumption ? wide power supply operating range of 3.0v to 5.5v ? available qml q or v processes ? 14-lead flatpack ? UT54ACS08E-smd-5962-96518 ? ut54acts08e-smd-5962-96519 function table description the UT54ACS08E and ut54acts 08e are quadruple two-in- put and gates. the circuits perform the boolean functions y= a ??? b or y = in positive logic. the devices are characterized ov er full hirel temperature range of -55 ? c to +125 ? c. pinout 14-pin flatpack top view logic diagram input output a b y h h h l x l x l l y1 (3) (6) y2 y3 (8) (11) y4 (1) a1 (2) b1 (4) a2 (5) b2 (9) a3 (10) b3 (12) a4 (13) b4 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. ? a + b 1 2 3 4 5 7 6 14 13 12 11 10 8 9 v dd b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 v ss b4 a4 y4 b3 a3 y3 a1 b1 y1 a2 b2 y2 logic symbol
2 operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings 1 note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond lim its indicated in the operational sections is not recommended. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. 2. per mil-std-883, method 1012.1, section 3.4.1, p d = (t j(max) - t c(max) ) / ? jc recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 ? c t j maximum junction temperature +175 ? c t ls lead temperature (soldering 5 seconds) +300 ? c ? jc thermal resistance junction to case 15.5 ? c/w i i dc input current ? 10 ma p d 2 maximum package power dissipation permitted @ tc=125 o c 3.2 w symbol parameter limit units v dd supply voltage 3.0 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to +125 ? c
3 dc electrical characteris tics for the UT54ACS08E 7 ( v dd = 3.0v to 5.5v; v ss = 0v 6 ; -55 ? c < t c < +125 ? c) symbol description condition min max unit v il low-level input voltage 1 v dd from 3.0v to 5.5v 0.3 v dd v v ih high-level input voltage 1 v dd from 3.0v to 5.5v 0.7 v dd v i in input leakage current v in = v dd or v ss -1 1 ? a v ol low-level output voltage 3 i ol = 100 ? a v dd from 3.0v to 5.5v 0.25 v v oh high-level output voltage 3 i oh = -100 ? a v dd from 3.0v to 5.5v v dd - 0.25 v i os1 short-circuit output current 2 ,4 v o = v dd and v ss, v dd from 4.5v to 5.5v -200 200 ma i os2 short-circuit output current 2 ,4 v o = v dd and v ss, v dd from 3.0v to 3.6v -100 100 ma i ol1 low level output current (sink) 9 v in = v dd or v ss v ol = 0.4v v dd from 4.5v to 5.5v 8 ma i ol2 low level output current (sink) 9 v in = v dd or v ss v ol = 0.4v v dd from 3.0v to 3.6v 6 ma i oh1 high level output current (source) 9 v in = v dd or v ss v oh = v dd -0.4v v dd from 4.5v to 5.5v -8 ma i oh2 high level output current (source) 9 v in = v dd or v ss v oh = v dd -0.4v v dd from 3.0v to 3.6v -6 ma p total1 power dissipation 2, 8 c l = 50pf, v dd = 4.5v to 5.5v 1 mw/ mhz
4 notes: 1. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density ? 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buffer) times fre quency should no t exceed 3,765pf/ mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifica tion and when design changes may affect th e value. capacitance is measured between the designated terminal and v ss at a frequency of 1mhz and a signa l amplitude of 50 mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose ? 1e6 rads(si) per mil-std-883 method 1019. 8. power dissipation specifi ed per switching output. 9. guaranteed by characterization, but not tested. p total2 power dissipation 2, 8 c l = 50pf, v dd = 3.0v to 3.6v 0.5 mw/ mhz i ddq quiescent supply current v in = v dd or v ss v dd from 3.0v to 5.5v 10 ? a c in input capacitance 5 ? = 1mhz v dd = 0v 15 pf c out output capacitance 5 ? = 1mhz v dd = 0v 15 pf
5 ac electrical characteristics for the UT54ACS08E 2 (v dd = 3.0v to 5.5v; v ss = 0v 1 , -55 ? c < t c < +125 ? c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications va lid for radiation dose ? 1e6 rads(si) per mil-std-883 method 1019. symbol parameter v dd minimum maximum unit t plh input to yn c l = 50pf 3.0v to 3.6v 2 15 ns 4.5v to 5.5v 1 9 t phl input to yn c l = 50pf 3.0v to 3.6v 2 19 ns 4.5v to 5.5v 1 9
6 dc electrical characteristics for the ut54acts08e 7 ( v dd = 3.0v to 5.5v; v ss = 0v 6 ; -55 ? c < t c < +125 ? c) notes: 1. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or sc hmitt compatible inputs. devices may be test ed using any input voltage within the abov e specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density ? 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buffer) times frequency should not exceed 3,765pf/ mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications va lid for radiation dose ? 1e6 rads(si) per mil-std-883 method 1019. 8. power does not include power contribution of any ttl output sink current 9. power dissipation specified per switching output. symbol description condition vdd min max unit v il low-level input voltage 1 3.0v 0.8 v 5.5v 0.8 v ih high-level input voltage 1 3.0v 2.0 v 5.5v 2.75 i in input leakage current v in = v dd or v ss 5.5v -1 1 ? a v ol low-level output voltage 3 i ol = 6ma 3.0v 0.4 v i ol = 8ma 4.5v 0.4 v v oh high-level output voltage 3 i oh = -6ma 3.0v 2.4 v i oh = -8ma 4.5v 3.15 v i os short-circuit output current 2 ,4 v o = v dd and v ss 3.0v -100 100 ma 5.5v -200 200 i ol low level output current v in = v dd or v ss v ol = 0.4v 3.0v 6 ma 5.5v 8 i oh high level output current v in = v dd or v ss v oh = v dd -0.4v 3.0v -6 ma 5.5v -8 p total power dissipation 2, 8, ,9 c l = 50pf 5.5v 1.8 mw/ mhz 3.0v 0.72 i ddq quiescent supply current v in = v dd or v ss 5.5v 10 ? a ? i ddq quiescent supply current delta for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz 0v 15 pf c out output capacitance 5 ? = 1mhz 0v 15 pf
7 ac electrical characteristics for the ut54acts08e 2 (v dd = 3.0v to 5.5v; v ss = 0v 1 , -55 ? c < t c < +125 ? c) notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications va lid for radiation dose ? 1e6 rads(si) per mil-std-883 method 1019. symbol parameter v dd minimum maximum unit t plh input to yn c l = 30pf 3.0v to 3.6v 1 10 ns 4.5v to 5.5v 1 6 c l = 50pf 3.0v to 3.6v 1 14 ns 4.5v to 5.5v 1 10 t phl input to yn c l = 30pf 3.0v to 3.6v 1 13 ns 4.5v to 5.5v 1 9 c l = 50pf 3.0v to 3.6v 1 17 ns 4.5v to 5.5v 1 13
8 packaging 1. all exposed metallized areas are gold plated electroplated nickel per mil-prf-38535. 2. the lid is electri cally connected to v ss . 3. lead finishes are in accordance with mil-p 38535. 4. dimension symbol is in accordance with m prf-38533. 5. lead position and colanarity are not measured figure 1. 14-lead flatpack
9 ordering information: UT54ACS08E and ut54acts08e: smd drawing number: 96518 = UT54ACS08E device type: 02 = 1 rad(si)/sec package type: x = 14-lead ceramic botto m-brazed dual-in-line flatpack lead finish: (notes 1 & 2) a = solder c = gold x = optional 5962 ***** ** * * * * total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) 03 = 50 to 300 rad(si)/sec class designator: q = qml class q v = qml class v 96519 = ut54acts08e notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2. device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si), and 5e5 rads(si), and is tested in accordance w ith mil-std-883 test method 1019 condition a.
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